1. Field of the Invention
This invention relates to a processing method by a pipeline control mode processor in which first instruction data are fetched during a first cycle and in which processing is executed on the basis of the first instruction data and second instruction data are fetched during the ensuing second cycle.
2. Description of the Prior Art
There have been heretofore extensively presented digital computers operating under the von Neumann type stored program system. With this type of the digital computers, the machine language instruction information data stored in a program storage section is selectively fetched by a sequencer and data processing is executed in accordance with the thus fetched instruction information data.
In general, in an assembler level conditional branching in a processor of a digital computer, there are required two different instructions, that is the conditional judgment instruction [CMP A, B], such as CMP A, B and the branching instruction [JMP(Z)****], such as JMP(Z) LABEL. The branching instruction gives a judgment on branching on the basis of the immediately preceding status of the processor. Since the branching itself is an instruction, at, least two instructions are necessitated.
When performing the conditional branching in the conventional digital computer, the data of the conditional judgment, instruction [CMP A, B] information (in the form of machine language instruction information data stored in the program storage section) is fetched and decoded by the sequencer. The operating section then gives a judgment on the condition in accordance with the judgment instruction [CMP, A, B] information and sets a flag, for example, indicating the result of judgment in a predetermined register. This terminates the processing for executing the conditional judgment instruction [CMP, A, B].
The sequencer then fetches and decodes the branching instruction [JMP(Z)****] (in the form of machine language instruction information data from the program storage section). The sequencer then makes a judgment, as to branching based on the flag set in the register and executes the processing for branching.
With the above described conventional digital computer, two instructions, namely the conditional judgment, instruction [CMP A, B] and branching instruction [JMP(Z)****], need to be provided and executed step by step by way of performing the processing for conditional branching.
On the other hand, in a processor of the pipeline type of the digital computer, the processing operation is divided into plural sections and processing for these sections is performed continuously in parallel similarly to an assembly line operation in accordance with a pipeline control mode to enable high speed processing.
For example, in a processor provided with two pipelines, when processing a series of instruction [1], [2], [3], . . . stating a predetermined program, as shown in FIG. 1 , the operation of fetching the data [1], [2], [3], . . . and the operation of executing processing in accordance with the fetched data [1], [2], [3], . . . are performed in parallel.
Meanwhile, when the following branching processing program
______________________________________ . . . move 3, r.o slashed. [1] jmp label [2] move r.o slashed., rl [3] . . . label: move 3, r.o slashed. [A] move 1, r.o slashed. [B] . . . ______________________________________
is executed on a processor having the two pipelines, the jump instruction [2] is executed during the time the instruction [3] following the jump instruction [2] is fetched, as shown in FIG. 2, such that, after the instruction [3] data, the instruction [A] data, specified by the label contained in the jump instruction [2] data, are fetched. Meanwhile, the instruction [3] data, next to the jump [2] data, is handled as what is called hop, for which no operation is performed.
Now suppose that, in the above described processor provided with the two pipelines, an interrupt demand is accepted and an interrupt is to be executed. If, with the instruction sequence of the interrupt service routine of [i.sub.l ], [i.sub.2 ], [i.sub.3 ], . . . the interrupt demand is made during execution of the instruction [2], as shown at FIG. 3A, the interrupt demand is accepted after execution of the instruction [2]. During the operating cycle in which the interrupt demand has been accepted, the address information of the instruction data of the interrupt service routine is read from a predetermined memory, while the return address data to the instruction [3] data fetched during the cycle of executing the instruction [2] is transiently saved or pushed in a stack register. From the next cycle on, the instruction [i.sub.1 ], [i.sub.2 ], [i.sub.3 ], . . . data of the interrupt service routine is fetched and executed. When returning from the interrupt service routine, the return instruction [ret] data are fetched once and the return adders data to the instruction [3] data are popped from the stack register during the cycle of execution of the return instruction [ret], as shown at in FIG. 3B. The instruction [3] data, as indicated by the address data, is fetched and executed.
With the conventional processor, operating in accordance with the above described pipeline control mode, should an interrupt demand be made during the execute cycle of the jump instruction [2], as shown in FIG. 3A, the return address data to the instruction [3] data fetched during the execute cycle of the jump instruction [2] is pushed into the stack register. Therefore, when returning from the interrupt service routine, the instruction [3] data is fetched and executed, based on the return address data to the instruction [3] data popped from the stack register, as shown in FIG. 3B, so that the jump instruction [2] data is disregarded as a practical matter. Thus the interrupt demand cannot be accepted during execution of the jump instruction data.
Meanwhile, in a virtual memory system with a processor operating under a pipeline control mode, should a so-called page fault occur during fetching of instruction data and hence an interrupt demand raised, it is necessary to accept the interrupt demand at the time point of termination of the execute cycle in accordance with instruction data fetched during the fetch cycle preceding the fetch cycle of the above mentioned instruction data before processing to execution of the interrupt service routine for page fault processing. However, if the instruction executed at the time of page fault occurrence is the jump instruction data, the interrupt demand cannot be accepted, as explained hereinabove. For this reason, it becomes impossible to proceed to the page fault processing.